Method for forming a metallization layer

ABSTRACT

A method for forming a metallization layer. A first layer is formed outwardly from a semiconductor substrate. Contact vias are formed through the first layer to the semiconductor substrate. A second layer is formed outwardly from the first layer. Portions of the second layer are selectively removed such that the remaining portion of the second layer defines the layout of the metallization layer and the contact vias. The first and second layers are electroplated by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers in a solution containing metal ions. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer. Further, metal ions deposited on the first layer during a positive duty cycle are removed from the first layer during a negative duty cycle. Finally, exposed portions of the first layer are selectively removed.

[0001] This application is a Divisional of U.S. application Ser. No.09/652,619, filed Aug. 31, 2000, which is a Continuation of U.S.application Ser. No. 08/912,051, filed Aug. 18, 1997, now U.S. Pat. No.6,144,095, which is a Continuation of U.S. application Ser. No.08/656,712, filed Jun. 3, 1996, now U.S. Pat. No. 5,662,788.

TECHNICAL FIELD OF THE INVENTION

[0002] The present invention relates generally to integrated circuitsand, in particular, to a method for forming a metallization layer.

BACKGROUND OF THE INVENTION

[0003] An integrated circuit comprises a large number of semiconductordevices, such as transistors, that are formed on a semiconductorsubstrate or, more colloquially, a “chip.” These devices are selectivelyinterconnected by one or more patterned layers of a conductive material,typically aluminum, to form a circuit that performs a desired function.These layers are referred to as “metallization” layers. As integratedcircuits become more complex, designers reduce the minimum feature sizeof the constituent devices of the circuit, so as to fit more devices ona chip. With this reduction in size, it becomes more difficult toachieve proper pattern definition using conventional techniques such asphotolithography and dry etch techniques for forming metallizationlayers. Further, designers have attempted to use copper instead ofaluminum as the principle metallization material in the metal-lizationlayers, due to perceived advantages in resistivity, ductility andmelting point. Unfortunately, developers have not been able to create areliable technique for patterning a copper layer.

[0004] For example, one process using electro-deposition for forming acopper metallization layer is described in U.S. Pat. No. 5,151,168.According to this process, a conductive barrier layer is deposited on asemiconductor substrate. Further, a photoresist reverse image of themaskwork normally used to etch the metallization pattern is created onthe substrate. The wafer is then transferred to an electrolytic bath inwhich the copper is complexed with EDTA molecules. A fixed voltage isapplied between a voltage source and the semiconductor substrate todeposit the copper ions on the barrier layer that is not covered by thephotoresist layer including contact/via openings on the semiconductorsubstrate. Unfortunately, when the substrate is placed in theelectrolytic bath, the photoresist material may lift-off from thesubstrate thus depositing copper in areas where it is not required.

[0005] For the reasons stated above, and for other reasons stated belowwhich will become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art fora method for forming a metallization layer that avoids the disadvantagesand problems of prior techniques.

SUMMARY OF THE INVENTION

[0006] A method for forming a metallization layer is described whichuses a single electro-deposition step to reliably form both themetallization layer and to fill the contact vias. In particular, oneembodiment of the present invention uses first and second layers ofmaterials that are placed at different surface potentials to form themetallization layer. The first layer is formed outwardly from asemiconductor substrate. Contact vias are formed through the first layerto the semiconductor substrate. The second layer is formed outwardlyfrom the first layer. Portions of the second layer are selectivelyremoved such that the remaining portion of the second layer defines thelayout of the metallization layer and the contact vias. Metal ions in asolution are electro-deposited by applying a bi-polar modulated voltagehaving a positive duty cycle and a negative duty cycle to the layers andthe solution. The voltage and surface potentials are selected such thatthe metal ions are deposited on the remaining portions of the secondlayer. Further, metal ions deposited on the first layer during apositive duty cycle are removed from the first layer during a negativeduty cycle. Finally, exposed portions of the first layer are selectivelyremoved.

[0007] In another embodiment of the present invention, the first andsecond layers are placed at different surface potentials by applying afirst voltage to a surface of the first layer and applying a secondvoltage, higher than the first voltage, to the second layer. In anotherembodiment of the present invention the different surface potentials areachieved in part by selecting materials for the first and second layersthat have different innate surface potentials.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIGS. 1A through 1D are cross-sectional views of a semiconductorsubstrate that illustrate process steps according to an illustrativeembodiment of the present invention.

[0009]FIGS. 2 and 3 are cross-sectional views of additional illustrativeembodiments of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0010] In the following detailed description of the invention, referenceis made to the accompanying drawings which form a part hereof, and inwhich is shown by way of illustration specific embodiments in which theinvention may be practiced. These embodiments are described insufficient detail to enable those skilled in the art to practice theinvention, and it is to be understood that other embodiments may be usedand that logical, mechanical and electrical changes may be made withoutdeparting from the spirit and scope of the present invention. Thefollowing detailed description is, therefore, not to be taken in alimiting sense.

[0011]FIGS. 1A through 1D are cross-sectional views of semiconductorsubstrate 10 that depict process steps according to an illustrativeembodiment of the present invention. Advantageously, the illustrativeembodiment forms a metallization layer, including filling contact vias,outwardly from semiconductor substrate 10 in a single electro-depositionstep. The process exposes adjacent layers of materials that are formedoutwardly from semiconductor substrate 10 with different surfacepotentials to a bi-polar modulated voltage source to deposit themetallization layer and to fill the contact vias. The surface potentialsand the modulated voltage are selected such that the metallization layerforms only on the second layer because metal that deposits on the firstlayer during a first duty cycle of the bi-polar modulated voltage isremoved from the first layer during a second duty cycle.

[0012] As shown in FIG. 1A, borophosphosilicate glass (BPSG) layer 12 isdeposited and reflowed outwardly from semiconductor substrate 10. Firstlayer 14 is formed outwardly from BPSG layer 12. First layer 14 maycomprise, for example, poly-silicon, doped or undoped, that is depositedusing a conventional chemical vapor deposition (CVD) or sputteringtechnique. Alternatively, other materials such as germanium may besubstituted for the poly-silicon. Contact via 16 is etched through firstlayer 14 and BPSG layer 12 to, for example, junction 18 of semiconductorsubstrate 10. Second layer 20 is formed outwardly from first layer 14 soas to line contact via 16 and cover first layer 14 by, for example,depositing a layer of titanium nitride or other appropriate barrierlayer material using a conventional sputter or chemical vapor depositiontechnique. First layer 14 and second layer 20 have a thickness on theorder of 100 to 500 Å. Advantageously, the innate surface potential offirst layer 14 is lower than the innate surface potential of secondlayer 20. This difference in surface potentials contributes to theselectivity of the electro-deposition step described below. In otherembodiments, first and second layers 14 and 20 can be fabricated fromother materials that provide similar differences in innate surfacepotential.

[0013] Portions of second layer 20 are selectively removed such that theremaining portions of second layer 20 match the desired pattern for themetallization layer, including contact vias. As shown in FIG. 1B, layer22, comprising, for example, a conventional photoresist material, isformed outwardly from layer 20 using conventional techniques. Layer 22is exposed through a mask. Portions of layer 22 are removed with asolvent so as to produce a patterned layer of photoresist material thatmatches the desired metallization layer. The exposed portions of layer20 are removed with, for example, a dry etch leaving a patterned versionof layer 20. Layer 22 is removed.

[0014] Once layer 20 is patterned, semiconductor substrate 10 is placedin an electrolytic bath for electro-deposition of the metallizationlayer outwardly from layer 20 so as to fill contact vias 16. The bathincludes metal ions in a solution. For example, the metal ions maycomprise copper ions in a solution as described in U.S. Pat. No.5,151,168 entitled “Process for Metallizing Integrated Circuits WithElectricallyDeposited Copper” (the “'168 patent”), the teachings ofwhich are incorporated by reference. Specifically, one embodiment of theelectrolytic bath is described in the '168 patent at Column 5, lines 10through 35. Alternatively, the electrolytic bath may comprise a solutioncontaining nickel or palladium ions.

[0015] Voltage source 26 provides a bipolar modulated voltage to anode28 and voltage source 24 provides a DC offset voltage to anode 28. Thevoltage on anode 28 causes metal ions to be deposited on a layer whenthe potential difference between anode 28 and the surface potential ofthe layer exceeds the reduction potential of the metal. Conversely, thevoltage on anode 28 causes metal ions to be removed from the surface ofa layer when the potential difference between anode 28 and the surfacepotential of the layer is less than the reverse deposition potential ofthe metal. The voltages of sources 26 and 28 are selected such thatmetal deposited on layer 14 during a first duty cycle is removed duringa second duty cycle. Further, metal is not removed from layer 20 duringthe second duty cycle. For example, in one embodiment source 26 providesa square wave with a dc offset provided by source 24 such that duringthe positive duty cycle of source 26, metal ions deposit on layers 14and 20 and during the negative duty cycle copper is etched from layer14. In other embodiments, source 26 comprises other time-varyingwave-forms such as a triangle wave, sinusoidal wave or other appropriatevoltage wave form.

[0016] Once the deposition of metallization layer 30 is complete,exposed portions of first layer 14 are removed leaving the structureshown in FIG. 1D. In one embodiment, metallization layer 30 covers allof the exposed surfaces of layer 20 as shown in FIG. 2. It is understoodthat an integrated circuit constructed according to this process wouldinclude a complete metallization layer with a plurality of contact viaseven though only portions of the metallization layer and a singlecontact via are shown in FIGS. 1A through 1D.

Conclusion

[0017] Although an illustrative embodiment has been described herein, itwill be appreciated by those of ordinary skill in the art that anyarrangement which is calculated to achieve the same purpose may besubstituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the illustrativeembodiment. For example, the type of modulated voltage can be variedfrom the specified square wave used in the illustrative embodiment.Further, the difference in surface potential between layers 14 and 20can be imposed or enhanced by applying voltages to the surfaces oflayers 14 and 20. In this embodiment, layers 14 and 20 are separated byinsulating layer 15 as shown in FIG. 3. The composition of theelectrolytic bath can be varied so long as metal ions deposit on layer20 when sources 24 and 26 are applied to anode 28.

What is claimed is:
 1. A method for forming a metallization layeroutwardly from a semiconductor substrate, the method comprising thesteps of: forming a first layer of a material outwardly from thesemiconductor substrate; forming contact vias that extend through thefirst layer to the semiconductor substrate; forming a layer of a secondmaterial outwardly from the first layer; selectively removing portionsof the second layer such that the remaining portion of the second layerdefines the layout of the metallization layer and the contact vias;placing the first and second layers at different surface potentials;electro-depositing the first and second layers in a solution of metalions by applying a bi-polar modulated voltage having a positive dutycycle and a negative duty cycle, the voltage and surface potentialsselected such that the metal is deposited on the remaining portions ofthe second layer and that metal deposited on the first layer during apositive duty cycle is removed from the first layer during a negativeduty cycle; and selectively removing exposed portions of the firstlayer.
 2. The method of claim 1, wherein the step of depositing a firstlayer comprises depositing a layer of poly-silicon outwardly from thesemiconductor substrate.
 3. The method of claim 1, wherein the step ofelectroplating comprises the steps of: depositing the semiconductorsubstrate in an electrolytic bath containing a metal having a reductionpotential; and exposing the bath to a modulated voltage such that duringa positive duty cycle the metal is deposited on exposed surfaces of thefirst layer and the second layer and that during a negative duty cyclethe metal is removed from the exposed surface of the first layer.
 4. Themethod of claim 1, wherein the step of depositing a second layercomprises depositing a layer of titanium nitride.
 5. The method of claim3, wherein the step of depositing the semiconductor substrate in anelectrolytic bath comprises the step of depositing the semiconductorsubstrate in an electrolytic bath containing copper ions.
 6. The methodof claim 1, wherein the step of placing the first and second layers atdifferent surface potentials comprises the step of applying a firstvoltage to a surface of the first layer and applying a second voltage,different than the first voltage, to the second layer, wherein the firstand second layers are separated by an insulating layer.
 7. The method ofclaim 1, wherein the step of placing the first and second layers atdifferent surface potentials comprises the step of selecting a materialfor the first layer that has an innate surface potential that is lessthan the innate surface potential for the material selected for thesecond layer.
 8. The method of claim 1, wherein the step ofelectroplating the first and second surfaces comprises the step ofelectroplating the first and second surfaces with a voltage source thatproduces a substantially square wave voltage output.
 9. A method forforming a metallization layer outwardly from a semiconductor substrate,the method comprising the steps of: forming a first layer of a materialoutwardly from the semiconductor substrate, the first layer having afirst innate surface potential; forming contact vias that extend throughthe first layer to the semiconductor substrate; forming a layer of asecond material outwardly from the first layer so as to line the contactvias and cover the first layer, the second layer having a second innatesurface potential different from said first innate surface potential;selectively removing portions of the second layer such that theremaining portion of the second layer defines the layout of themetallization layer and the contact vias; placing the semiconductorsubstrate with the first and second layers in an electrolytic bathcomprising a solution of metal ions; applying a bi-polar modulatedvoltage having a positive duty cycle and a negative duty cycle to theelectrolytic bath, the voltage and surface potentials selected such thatthe metal is deposited on the remaining portions of the second layer andthat metal deposited on the first layer during a positive duty cycle isremoved from the first layer during a negative duty cycle; andselectively removing exposed portions of the first layer.
 10. The methodof claim 9, wherein the step of depositing a first layer comprisesdepositing a layer of poly-silicon outwardly from the semiconductorsubstrate.
 11. The method of claim 9, wherein the step of placing thesemiconductor substrate with the first and second layers in anelectrolytic bath comprises the step of placing the semiconductorsubstrate with the first and second layers in an electrolytic bathcontaining copper ions in solution.
 12. The method of claim 9, whereinthe step of depositing a second layer comprises depositing a layer oftitanium nitride.
 13. The method of claim 9, and further comprising thestep of imposing an external voltage to one of the first and secondlayers to place the first and second layers at different surfacepotentials.
 14. The method of claim 9, and further comprising the stepof placing the first and second layers at different surface potentialsby applying a first voltage to a surface of the first layer and applyinga second voltage, different from the first voltage, to the second layer,wherein the first and second layers are separated by an insulatinglayer.
 15. The method of claim 9, wherein the step of electroplating thefirst and second surfaces comprises the step of electroplating the firstand second surfaces with a voltage source that produces a substantiallysquare wave voltage output.
 16. An integrated circuit, comprising: aplurality of semiconductor devices formed on a semiconductor substrate;a metallization layer formed outwardly from the semiconductor substratethat selectively interconnects the semiconductor devices so as to beoperable to perform a function; a first patterned layer of materialformed outwardly from the semiconductor substrate that matches themetallization pattern; and a second patterned layer of material, formedbetween the metallization layer and the first patterned layer, thatmatches the metallization pattern and lines contact vias that extendthrough the first layer to the semiconductor substrate.
 17. Theintegrated circuit of claim 16, wherein the metallization layercomprises copper deposited on the second layer in an electrolytic bath.18. The integrated circuit of claim 16, wherein the first layercomprises poly-silicon.
 19. The integrated circuit of claim 16, whereinthe second layer comprises titanium nitride.
 20. The integrated circuitof claim 16, wherein the metallization layer comprises copper.
 21. Amethod of forming an integrated circuit, comprising: providing asemiconductor substrate; forming a first layer overlying the substrate;forming a second layer overlying the first layer to form an exposedfirst layer and an exposed second layer; depositing metal ions on theexposed first layer and on the exposed second layer by applying a firstvoltage between the substrate and an anode in the presence of anelectrolytic bath; and removing metal ions from the exposed first layerby applying a second voltage between the substrate and the anode in thepresence of the electrolytic bath.
 22. The method of claim 21, whereinforming the first layer overlying the substrate includes forming contactvias that extend through the first layer to the substrate.
 23. Themethod of claim 21, wherein the metal ions include copper ions.
 24. Themethod of claim 21, wherein the metal ions include nickel ions.
 25. Themethod of claim 21, wherein the metal ions include palladium ions. 26.The method of claim 21, further comprising forming an insulator betweenthe first layer and the second layer, and providing a first potential onthe first layer and a second potential on the second layer.
 27. Themethod of claim 21, wherein the first layer has a first surfacepotential and the second surface has a second surface potential.
 28. Amethod of forming an integrated circuit, comprising: providing asemiconductor substrate; depositing a first layer overlying thesubstrate; depositing a second layer; patterning the second layer tocorrespond with a desired metallization layer, the patterned secondlayer forming an exposed second layer and revealing an exposed firstlayer portion; depositing metal ions on the exposed first layer portionand on the exposed second layer by applying a first voltage between thesubstrate and an anode in the presence of an electrolytic bath; andremoving metal ions from the exposed first layer portion by applying asecond voltage between the substrate and the anode in the presence ofthe electrolytic bath.
 29. The method of claim 28, wherein the metalions include copper ions.
 30. The method of claim 28, wherein the metalions include nickel ions.
 31. The method of claim 28, wherein the metalions include palladium ions.
 32. The method of claim 28, furthercomprising depositing an insulator layer between the first layer and thesecond layer, and providing a first potential on the first layer and asecond potential on the second layer.
 33. The method of claim 28,wherein the first layer has a first surface potential and the secondsurface has a second surface potential.
 34. A method of forming anintegrated circuit, comprising: providing a partially-formedsemiconductor device having: a substrate; a first layer overlying thesubstrate; a second layer overlying the first layer, wherein the devicehas an exposed first layer and an exposed second layer; and providing abi-polar modulated voltage between the substrate and an anode in thepresence of an electrolytic bath containing metal ions, wherein themodulated voltage has a first duty cycle and a second duty cycle;wherein the metal ions are deposited on the exposed first layer and theexposed second layer during the first duty cycle; and wherein the metalions are removed from the exposed first layer during the second dutycycle.
 35. The method of claim 34, wherein the first layer comprisespolysilicon and the second layer comprises titanium nitride.
 36. Themethod of claim 34, wherein the first duty cycle includes a positiveduty cycle and the second duty cycle includes a negative duty cycle. 37.The method of claim 34, wherein the metal ions include copper ions. 38.The method of claim 34, wherein the metal ions include nickel ions. 39.The method of claim 34, wherein the metal ions include palladium ions.40. The method of claim 34, wherein the partially-formed semiconductordevice has an insulator layer between the first layer and the secondlayer, the method further comprising providing a first potential on thefirst layer and a second potential on the second layer.
 41. The methodof claim 34, wherein the first layer has a first surface potential andthe second surface has a second surface potential.
 42. A method offorming an integrated circuit, comprising: providing a semiconductorsubstrate; forming a first layer overlying the substrate; forming asecond layer overlying the first layer, wherein the first layer includesan exposed first layer and the second layer includes an exposed secondlayer; depositing metal ions on the exposed first layer and on theexposed second layer by applying a first voltage between the substrateand an anode in the presence of an electrolytic bath; and removing metalions from the exposed first layer by applying a second voltage betweenthe substrate and the anode in the presence of the electrolytic bath.43. The method of claim 42, wherein the first layer has a first surfacepotential and the second surface has a second surface potential.
 44. Themethod of claim 42, further comprising forming an insulating layerbetween the first layer and the second layer, and providing a firstpotential on the first layer and a second potential on the second layer.45. The method of claim 42, wherein the metal ions include copper ions.46. The method of claim 42, wherein the metal ions include nickel ions.47. The method of claim 42, wherein the metal ions include palladiumions.
 48. A method of forming an integrated circuit, comprising:providing a substrate; providing a first layer overlying the substrate,wherein the first layer has contact vias; forming a second layer,wherein the second layer lines the contact vias; patterning the secondlayer revealing an exposed first layer portion; and performing a singleelectro-deposition step to form a metallization layer and fill thecontact vias, including using a bipolar modulated voltage to depositmetal ions on the exposed first layer portion and on the second layerduring a first duty cycle and removing metal ions from the exposed firstlayer during a second duty cycle.
 49. The method of claim 48, whereinthe first layer has a first surface potential and the second layer has asecond surface potential.
 50. The method of claim 48, further comprisingproviding an insulator layer between the first layer and the secondlayer, and applying a first potential to the first layer and a secondpotential to the second layer.
 51. A method for depositing metal on asemiconductor device having a substrate, an exposed first surface, andan exposed second surface, comprising: depositing metal ions on theexposed first surface and on the exposed second layer by applying afirst voltage between the substrate and an anode in the presence of anelectrolytic bath; and removing metal ions from the exposed firstsurface by applying a second voltage between the substrate and the anodein the presence of the electrolytic bath.
 52. The method of claim 51,wherein the exposed first surface has a first potential and the exposedsecond surface has a second potential.
 53. The method of claim 51,wherein the semiconductor device includes an insulator layer between thefirst layer and the second layer, the method further comprising placinga first potential on the first layer and placing a second potential onthe second layer.
 54. The method of claim 51, wherein the metal ionsinclude copper ions.
 55. The method of claim 51, wherein applying afirst voltage and applying a second voltage includes applying a bipolarmodulated voltage between the substrate and the anode.
 56. A method fordepositing copper on a semiconductor device having a substrate, anexposed first surface, and an exposed second surface, comprising:providing a voltage with a positive duty cycle between the substrate andan anode in the presence of an electrolytic bath containing copper ionsto deposit the copper ions on the exposed first layer and the exposedsecond layer during the positive duty cycle; and providing a voltagewith a negative duty cycle between the substrate and an anode in thepresence of the electrolytic bath to remove the copper ions from theexposed first layer during the negative duty cycle.
 57. The method ofclaim 56, wherein the exposed first surface has a first potential andthe exposed second surface has a second potential.
 58. The method ofclaim 56, wherein the semiconductor device includes an insulator layerbetween the first layer and the second layer, the method furthercomprising placing a first potential on the first layer and placing asecond potential on the second layer.
 59. The method of claim 56,wherein the first layer comprises polysilicon and the second layercomprises titanium nitride.